Efficient instruction scheduling using finite state automata
Proceedings of the 28th annual international symposium on Microarchitecture
Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
Application specific compiler/architecture codesign: a case study
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Compiler Design Issues for Embedded Processors
IEEE Design & Test
FlexWare: A Retargetable Embedded-Software Development Environment
IEEE Design & Test
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions
Proceedings of the 12th international symposium on System synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
C Compiler Retargeting Based on Instruction Semantics Models
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Automatic instruction scheduler retargeting by reverse-engineering
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Processor Description Languages
Processor Description Languages
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Hi-index | 0.00 |
The availability of C compilers is crucial to the efficient design of embedded systems. Using virtual resources to automatically generate parts of a compiler脮s instruction scheduler from a formal processor description significantly reduces the overall scheduler generation time.