Application specific compiler/architecture codesign: a case study
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Compiler Design Issues for Embedded Processors
IEEE Design & Test
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Synthesizable HDL generation method for configurable VLIW processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Processor/Memory Co-Exploration on Multiple Abstraction Levels
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 42nd annual Design Automation Conference
A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures
Journal of VLSI Signal Processing Systems
Designing real-time H.264 decoders with dataflow architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Design and implementation of a modular and portable IEEE 754 compliant floating-point unit
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Generic netlist representation for system and PE level design exploration
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Journal of VLSI Signal Processing Systems
Design space exploration of partially re-configurable embedded processors
Proceedings of the conference on Design, automation and test in Europe
Multimedia terminal system-on-chip design and simulation
EURASIP Journal on Applied Signal Processing
ACM Transactions on Embedded Computing Systems (TECS)
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Proceedings of the 45th annual Design Automation Conference
A versatile generator of instruction set simulators and disassemblers
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
A compiler framework for the reduction of worst-case execution times
Real-Time Systems
Design Methodology for Offloading Software Executions to FPGA
Journal of Signal Processing Systems
Tuning a protocol processor architecture towards DSP operations
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case
Journal of Systems Architecture: the EUROMICRO Journal
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The development of application-specific instruction-set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expertise in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be generated automatically including high-level language C compiler, assembler, linker, simulator, and debugger frontend. Moreover, for architecture implementation, synthesizable hardware description language code can be derived, which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for digital video broadcasting terrestrial acquisition and tracking algorithms designed with the presented methodology are given. To show the quality of the generated software development tools, they are compared in speed and functionality with commercially available tools of state-of-the-art digital signal processor and μC architectures