Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A joined architecture/compiler design environment for ASIPs
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
A framework for fast hardware-software co-simulation
Proceedings of the conference on Design, automation and test in Europe
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Retargetable Code Generation for Digital Signal Processors
Retargetable Code Generation for Digital Signal Processors
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Automatic Generation of Microarchitecture Simulators
ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Analysis of the influence of register file size on energy consumption, code size, and execution time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Feedback driven instruction-set extension
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
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This paper proposes an architecture exploration methodology for application specific instruction set processors (ASIPs) including a C compiler and a VHDL model in the exploration loop. For a given application the target architecture is an instance of the scalable ALICE VLIW architecture which will be presented in this paper. In a case study it will be explained how the LISA processor design platform in conjunction with the CoSy compiler environment significantly reduces the time for exploration cycles. Using a typical telecommunications application, the quality of the resulting architecture and its performance are compared to the ICORE2 processor - a manually designed ASIP for efficient processing of computation intensive kernels.