MIPS RISC architecture
Design Automation for Embedded Systems
MetaCore: an application-specific programmable DSP development system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Application specific compiler/architecture codesign: a case study
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Instruction Scheduler Generation for Retargetable Compilation
IEEE Design & Test
Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
An SoC architecture and its design methodology using unifunctional heterogeneous processor array
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Novel architecture for loop acceleration: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Overview of the MPSoC design challenge
Proceedings of the 43rd annual Design Automation Conference
Rapid prototyping of JPEG encoder using the ASIP development system: PEAS-III
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Embedded DSP Processor Design: Application Specific Instruction Set Processors
Processor Description Languages
Processor Description Languages
NoGAP: A Micro Architecture Construction Framework
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
High-level design and validation of the BlueSPARC multithreaded processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Enabling large decoded instruction loop caching for energy-aware embedded processors
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A Structural Customization Approach for Low Power Embedded Systems Design
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
A power-driven multiplication instruction-set design method for ASIPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
Generating interlocked instruction pipelines from specifications of instruction sets
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems
International Journal of Handheld Computing Research
DLIC: Decoded loop instructions caching for energy-aware embedded processors
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large design space exploration and effectiveness of the system have been confirmed through experiments using several subsets of MIPS R3000 instruction set.