EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware/software instruction set configurability for system-on-chip processors
Proceedings of the 38th annual Design Automation Conference
ARM Architecture Reference Manual
ARM Architecture Reference Manual
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
PEAS-III: An ASIP Design Environment
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Programming Language Design Concepts
Programming Language Design Concepts
Computer Systems Design and Architecture (2nd Edition)
Computer Systems Design and Architecture (2nd Edition)
Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores (Systems on Silicon)
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
ViDL: A Versatile ISA Description Language
ECBS '12 Proceedings of the 2012 IEEE 19th International Conference and Workshops on Engineering of Computer-Based Systems
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The development of application specific processors (ASIPs) for systems-on-a-chip (SoCs) became increasingly popular in recent years. To efficiently develop such processors, respective tools are crucial. This paper presents methods to generate pipelined processors from a bare instruction set specification in ViDL. All microarchitectural aspects of the processor are contributed by a generator. Hazard resolution by forwarding, interlocking and branch prediction is automatically derived from instruction semantics, information on the targeted chip technology and an user supplied timing constraint. By variation of the latter, a set of compatible processor implementations is generated with different physical and dynamic characteristics. The processor generator has been evaluated using realistic instruction sets, such as ARM, MIPS, Power, SRC, DNACore and CoreVA. The generated processors have been tested on register-transfer-level and gate-level. In total, 83 processors have been generated and synthesized for a 65 nm STM low power technology, yielding clock frequencies of 260 - 680MHz for 2 - 7 stage pipelines. Clock frequency and the number of cycles per instruction (CPI) is similar to handcrafted designs.