Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Viewing instruction set design as an optimization problem
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Using a computer to design computer instruction sets
Using a computer to design computer instruction sets
Verification of configurable processor cores
Proceedings of the 37th Annual Design Automation Conference
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Evaluation of processor code efficiency for embedded systems
ICS '01 Proceedings of the 15th international conference on Supercomputing
Estimation of speed, area, and power of parameterizable, soft IP
Proceedings of the 38th annual Design Automation Conference
Automated design of finite state machine predictors for customized processors
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
A self-optimizing embedded microprocessor using a loop table for low power
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Tuning of loop cache architectures to programs in embedded system design
Proceedings of the 15th international symposium on System Synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Instruction generation for hybrid reconfigurable systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Polymorphous Computing Fabric
IEEE Micro
Embedded Computing: New Directions in Architecture and Automation
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Computer
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Instruction encoding synthesis for architecture exploration using hierarchical processor models
Proceedings of the 40th annual Design Automation Conference
Xtensa with User Defined DSP Coprocessor Microarchitectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Processors for Mobile Applications
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Power-efficient flexible processor architecture for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Proceedings of the conference on Design, automation and test in Europe - Volume 1
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
IEEE Transactions on Computers
Multiobjective Design of Embedded Processors on FPGA Platforms
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
A novel approach for flexible and consistent ADL-driven ASIP design
Proceedings of the 41st annual Design Automation Conference
Characterizing embedded applications for instruction-set extensible processors
Proceedings of the 41st annual Design Automation Conference
Design space exploration of caches using compressed traces
Proceedings of the 18th annual international conference on Supercomputing
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Energy Estimation for Extensible Processors
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Rapid Configuration and Instruction Selection for an ASIP: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A low power architecture for embedded perception
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Balancing design options with Sherpa
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Scalable custom instructions identification for instruction-set extensible processors
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Quick Reconfiguration in Clustered Micro-Sequencer
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs
IEEE Transactions on Computers
Smart diagnostics for configurable processor verification
Proceedings of the 42nd annual Design Automation Conference
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Satisfying real-time constraints with custom instructions
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
REMIC: design of a reactive embedded microprocessor core
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
New decompilation techniques for binary-level co-processor generation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
High-quality ISA synthesis for low-power cache designs in embedded microprocessors
IBM Journal of Research and Development
Exploiting forwarding to improve data bandwidth of instruction-set extensions
Proceedings of the 43rd annual Design Automation Conference
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CReconfigurable finite field instruction set architecture
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 17th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Architecture and Development Flow of the S5 Software Configurable Processor
Journal of VLSI Signal Processing Systems
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform
Proceedings of the conference on Design, automation and test in Europe
Instruction-set customization for real-time embedded systems
Proceedings of the conference on Design, automation and test in Europe
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Customizing multiprocessor implementation of an automated video surveillance system
EURASIP Journal on Embedded Systems
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Application driven embedded system design: a face recognition case study
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
An efficient framework for dynamic reconfiguration of instruction-set customization
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Integration, the VLSI Journal
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Code compression for VLIW embedded systems using a self-generating table
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic architecture refinement techniques for customizing processing elements
Proceedings of the 45th annual Design Automation Conference
Challenges: automated design of networking protocols
Proceedings of the 14th ACM international conference on Mobile computing and networking
Evaluation of ASIPs Design with LISATek
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Interconnect customization for a hardware fabric
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Processor Description Languages
Processor Description Languages
Intel® atom™ processor core made FPGA-synthesizable
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Playing the trade-off game: Architecture exploration using Coffeee
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction set extensions for software defined radio
Microprocessors & Microsystems
A memory system design framework: creating smart memories
Proceedings of the 36th annual international symposium on Computer architecture
Energy-performance Exploration of a CGA-based SDR Processor
Journal of Signal Processing Systems
Run-time reconfigurability in embedded multiprocessors
ACM SIGARCH Computer Architecture News
The design of a bloom filter hardware accelerator for ultra low power systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Runtime Adaptive Extensible Embedded Processors -- A Survey
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Fast enumeration of maximal valid subgraphs for custom-instruction identification
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Scalable register bypassing for FPGA-based processors
Microprocessors & Microsystems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Using a configurable processor generator for computer architecture prototyping
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Profiling-based hardware/software co-exploration for the design of video coding architectures
IEEE Transactions on Circuits and Systems for Video Technology
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Boosting AES performance on a tiny processor core
CT-RSA'08 Proceedings of the 2008 The Cryptopgraphers' Track at the RSA conference on Topics in cryptology
Selecting profitable custom instructions for reconfigurable processors
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
What is a configurable, extensible processor?
ACM SIGDA Newsletter
What is a configurable, extensible processor?
ACM SIGDA Newsletter
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Code transformations for embedded reconfigurable computing architectures
GTTSE'09 Proceedings of the 3rd international summer school conference on Generative and transformational techniques in software engineering III
Co-synthesis of FPGA-based application-specific floating point simd accelerators
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A polynomial-time custom instruction identification algorithm based on dynamic programming
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
An efficient algorithm for custom instruction enumeration
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Enforcing architectural contracts in high-level synthesis
Proceedings of the 48th Design Automation Conference
Shared reconfigurable fabric for multi-core customization
Proceedings of the 48th Design Automation Conference
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Compiler-driven leakage energy reduction in banked register files
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Exact custom instruction enumeration for extensible processors
Integration, the VLSI Journal
Sparse matrix-vector multiply on the HICAMP architecture
Proceedings of the 26th ACM international conference on Supercomputing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generating interlocked instruction pipelines from specifications of instruction sets
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Convolution engine: balancing efficiency & flexibility in specialized computing
Proceedings of the 40th Annual International Symposium on Computer Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid simulation for extensible processor cores
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Accelerating an application domain with specialized functional units
ACM Transactions on Architecture and Code Optimization (TACO)
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
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System designers can optimize Xtensa for their embedded application by sizing and selecting features and adding new instructions. Xtensa provides an integrated solution that allows easy customization of both hardware and software. This process is simple, fast, and robust.