ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Effectiveness of the ASIP design system PEAS-III in design of pipelined processors
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Architecture Implementation Using the Machine Description Language LISA
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models
Proceedings of the conference on Design, automation and test in Europe - Volume 2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ASIP architecture exploration for efficient IPSec encryption: A case study
ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005
Proceedings of the conference on Design, automation and test in Europe
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)
Proceedings of the 45th annual Design Automation Conference
Processor Description Languages
Processor Description Languages
Integrated verification approach during ADL-driven processor design
Microelectronics Journal
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Automatic multithreaded pipeline synthesis from transactional datapath specifications
Proceedings of the 47th Design Automation Conference
Automatic pipelining from transactional datapath specifications
Proceedings of the Conference on Design, Automation and Test in Europe
High-level design and validation of the BlueSPARC multithreaded processor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
An automatic energy consumption characterization of processors using ArchC
Journal of Systems Architecture: the EUROMICRO Journal
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Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hardware implementation. For this reason, design parameters such as timing, area or power consumption cannot be taken into consideration accurately during design space exploration. Design automation tools currently used to bridge this gap are either limited in the .exibility provided or only generate fragments of the architecture. This paper presents a synthesis tool which preserves the full flexibility of the architecture description language LISA, while being able to generate the complete architecture on RT-level using SystemC. This paper also presents two real world architecture case studies to prove the feasibility of our approach.