RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
Synthesizable HDL generation method for configurable VLIW processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A framework for systematic validation and debugging of pipeline simulators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 41st annual Design Automation Conference
Processor Description Languages
Processor Description Languages
Automatic generation of memory interfaces
SOC'09 Proceedings of the 11th international conference on System-on-chip
Automatic performance model synthesis from hardware verification models
Proceedings of the 2nd ACM/SPEC International Conference on Performance engineering
Automatic Generation of Memory Interfaces for ASIPs
International Journal of Embedded and Real-Time Communication Systems
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As embedded systems continue to face increasinglyhigher performance requirements, deeply pipelined processorarchitectures are being employed to meet desired systemperformance. System architects critically need modelingtechniques to rapidly explore and evaluate candidatearchitectures based on area, power, and performance constraints.We present an exploration framework for pipelinedprocessors. We use the EXPRESSION Architecture DescriptionLanguage (ADL) to capture a wide spectrum of processorarchitectures. The ADL has been used to enable performancedriven exploration by generating a software toolkitfrom the ADL specification. In this paper, we present afunctional abstraction technique to automatically generatesynthesizable RTL from the ADL specification. Automaticgeneration of RTL enables rapid exploration of candidatearchitectures under given design constraints such as area,clock frequency, power, and performance. Our explorationresults demonstrate the power of reuse in composing heterogeneousarchitectures using functional abstraction primitivesallowing for a reduction in the time for specificationand exploration by at least an order of magnitude.