ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
RSP '03 Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP'03)
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Techniques for accurate performance evaluation in architecture exploration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Processor/Memory Co-Exploration on Multiple Abstraction Levels
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimized ASIP Synthesis from Architecture Description Language Models
Optimized ASIP Synthesis from Architecture Description Language Models
Processor Description Languages
Processor Description Languages
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With the growing market for multiprocessor system-on-chip (MPSoC) solutions, application-specific instrucdon-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the Interfaces of dedicated memories or memory controllers, slowing down the design space exploration regarding the memory architecture. In order to overcome this drawback, this work extends RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols.