Processor Modeling for Hardware Software Codesign

Retargetable compiled simulation of embedded processors using a machine description language

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description

Proceedings of the 14th international symposium on Systems synthesis

Functional abstraction driven design space exploration of heterogeneous programmable architectures

Proceedings of the 14th international symposium on Systems synthesis

Retargetable cache simulation using high level processor models

ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture

Retargetable Program Profiling Using High Level Processor Models

HiPC '01 Proceedings of the 8th International Conference on High Performance Computing

DiST: a simple, reliable and scalable method to significantly reduce processor architecture simulation time

SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

RTL Processor Synthesis for Architecture Exploration and Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 3

Modeling and validation of pipeline specifications

ACM Transactions on Embedded Computing Systems (TECS)

Processor-memory coexploration using an architecture description language

ACM Transactions on Embedded Computing Systems (TECS)

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

ASIP architecture exploration for efficient IPSec encryption: A case study

ACM Transactions on Embedded Computing Systems (TECS) - SPECIAL ISSUE SCOPES 2005

Processor Description Languages

Processor Description Languages

A versatile generator of instruction set simulators and disassemblers

SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems

Automatic generation of memory interfaces

SOC'09 Proceedings of the 11th international conference on System-on-chip

Harmless, a hardware architecture description language dedicated to real-time embedded system simulation

Journal of Systems Architecture: the EUROMICRO Journal

Using the CASM language for simulator synthesis and model verification

Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Automatic Generation of Memory Interfaces for ASIPs

International Journal of Embedded and Real-Time Communication Systems