Communications of the ACM
Generation of software tools from processor descriptions for hardware/software codesign
DAC '97 Proceedings of the 34th annual Design Automation Conference
A processor desription language supporting retargetable multi-pipeline DSP program development tools
Proceedings of the 11th international symposium on System synthesis
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A methodology for accurate performance evaluation in architecture exploration
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A generic tool set for application specific processor architectures
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Facile: a language and compiler for high-performance processor simulators
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
Processor Modeling for Hardware Software Codesign
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A survey on modeling issues using the machine description language LISA
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Proceedings of the 40th annual Design Automation Conference
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Memory access optimizations in instruction-set simulators
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
High Speed CPU Simulation Using LTU Dynamic Binary Translation
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
Innovations in Systems and Software Engineering
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Instruction set simulators are indispensable tools for both the design of programmable architectures and software development. However, due to a constantly increasing processor complexity and the frequent demand for cycle-accurate models, such simulators have become defectively slow. The principle of compiled simulation addresses this shortcoming. Compiled simulators make use of a priori knowlegde to accelerate simulation, with the highest efficiency achieved by employing static scheduling techniques.In the past, such statically scheduled simulators have only been implemented for specific DSP architectures. The approach presented here discusses the application of static scheduling techniques to retargetable simulation tools based on the processor description language LISA. Principles and implementation issues are discussed in this paper, and results are presented for two selected processor architectures.