Iterative cache simulation of embedded CPUs with trace stripping
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Proceedings of the 14th international symposium on Systems synthesis
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
CalmRISC": A Low Power Microcontroller with Efficient Coprocessor Interface
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 42nd annual Design Automation Conference
Resource conflict detection in simulation of function unit pipelines
Journal of Systems Architecture: the EUROMICRO Journal
Resource conflict detection in simulation of function unit pipelines
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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This paper proposes a rapid evaluation scheme of pipeline architecture using phase-accurate simulation with only delay model and trace. With latency information for every stage, we can decide if an instruction in one stage can proceed to the next stage or if an instruction can be issued for each cycle without evaluating the value for registers. Branch target becomes available with trace generated by fast instruction set simulation. Fast verification time becomes possible because instruction set simulation is performed only once.