Communication architecture based power management for battery efficient system design
Proceedings of the 39th annual Design Automation Conference
Communication-Based Power Management
IEEE Design & Test
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Fast system-level power profiling for battery-efficient system design
Proceedings of the tenth international symposium on Hardware/software codesign
Mapping and Scheduling for Architecture Exploration of Networking SoCs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SystemC
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
System Design for DSP Applications Using the MASIC Methodology
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Analyzing On-Chip Communication in a MPSoC Environment
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Architecture-Level Performance Estimation for IP-Based Embedded Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
OCCN: A Network-On-Chip Modeling and Simulation Framework
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Hardware-Software Co-Design of Resource Constrained Systems on a Chip
ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7
OCCN: a NoC modeling framework for design exploration
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
System design for DSP applications in transaction level modeling paradigm
Proceedings of the 41st annual Design Automation Conference
Rate analysis for streaming applications with on-chip buffer constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient exploration of on-chip bus architectures and memory allocation
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
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A flexible framework for communication evaluation in SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Scheduler implementation in MP SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A formal method for hardware IP design and integration under I/O and timing constraints
ACM Transactions on Embedded Computing Systems (TECS)
Journal of VLSI Signal Processing Systems
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
Journal of Systems Architecture: the EUROMICRO Journal
Performance analysis of multimedia applications using correlated streams
Proceedings of the conference on Design, automation and test in Europe
Power macromodeling of MPSoC message passing primitives
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Performance estimation of distributed real-time embedded systems by discrete event simulations
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
A framework for system-level modeling and simulation of embedded systems architectures
EURASIP Journal on Embedded Systems
Arbiter synthesis approach for SoC multi-processor systems
Computers and Electrical Engineering
Application-specific workload shaping in multimedia-enabled personal mobile devices
ACM Transactions on Embedded Computing Systems (TECS)
Run-time integration of reconfigurable video processing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
ACM Transactions on Embedded Computing Systems (TECS)
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
Journal of Signal Processing Systems
IEEE Transactions on Circuits and Systems for Video Technology
Microprocessors & Microsystems
Communication architecture simulation on the virtual synchronization framework
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Analysis of a reconfigurable network processor
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A fast and effective dynamic trace-based method for analyzing architectural performance
Proceedings of the 16th Asia and South Pacific Design Automation Conference
The Lotterybus on-chip communication architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Transactions on Embedded Computing Systems (TECS)
Modeling noc architectures by means of deterministic and stochastic petri nets
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
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This paper presents a novel system-level performance analysis technique to support the design of custom communication architectures for system-on-chip integrated circuits. Our technique fills a gap in existing techniques for system-level performance analysis, which are either too slow to use in an iterative communication architecture design framework (e.g., simulation of the complete system) or are not accurate enough to drive the design of the communication architecture (e.g., techniques that perform a “static” analysis of the system performance). Our technique is based on a hybrid trace-based performance-analysis methodology in which an initial cosimulation of the system is performed with the communication described in an abstract manner (e.g., as events or abstract data transfers). An abstract set of traces are extracted from the initial cosimulation containing necessary and sufficient information about the computations and communications of the system components. The system designer then specifies a communication architecture by: 1) selecting a topology consisting of dedicated as well as shared communication channels (shared buses) interconnected by bridges; 2) mapping the abstract communications to paths in the communication architecture; and 3) customizing the protocol used for each channel. The traces extracted in the initial step are represented as a communication analysis graph (CAG) and an analysis of the CAG provides an estimate of the system performance as well as various statistics about the components and their communication. Experimental results indicate that our performance-analysis technique achieves accuracy comparable to complete system simulation (an average error of 1.88%) while being over two orders of magnitude faster