VLSI array processors
SIGGRAPH '95 Proceedings of the 22nd annual conference on Computer graphics and interactive techniques
YAPI: application modeling for signal processing systems
Proceedings of the 37th Annual Design Automation Conference
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Computers as components: principles of embedded computing system design
Computers as components: principles of embedded computing system design
Multiple view geometry in computer vision
Multiple view geometry in computer vision
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
GPU algorithms for radiosity and subsurface scattering
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Real-time rendering of translucent meshes
ACM Transactions on Graphics (TOG)
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
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Journal of VLSI Signal Processing Systems
Real-time GPU rendering of piecewise algebraic surfaces
ACM SIGGRAPH 2006 Papers
Cell broadband engine architecture and its first implementation: a performance view
IBM Journal of Research and Development
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International Journal of Parallel Programming
Queue - GPU Computing
A motion-adaptive deinterlacer via hybrid motion detection and edge-pattern recognition
Journal on Image and Video Processing - Regular
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IEEE Micro
DVFS Aware Techniques on Parallel Architecture Core (PAC) Platform
ICESSSYMPOSIA '08 Proceedings of the 2008 International Conference on Embedded Software and Systems Symposia
Multiresolution-Based Texture Adaptive Algorithm for High-Quality Deinterlacing
IEICE - Transactions on Information and Systems
Real-time Visual Tracker by Stream Processing
Journal of Signal Processing Systems
Journal of Signal Processing Systems
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Journal of Signal Processing Systems
Parallel Scalability of Video Decoders
Journal of Signal Processing Systems
Journal of Signal Processing Systems
IEEE Transactions on Multimedia
Algorithm/Architecture Co-Design of 3-D Spatio–Temporal Motion Estimation for Video Coding
IEEE Transactions on Multimedia
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiprocessor System-on-Chip (MPSoC) Technology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Image classification for content-based indexing
IEEE Transactions on Image Processing
Multiple motion segmentation with level sets
IEEE Transactions on Image Processing
Spatiotemporal video segmentation based on graphical models
IEEE Transactions on Image Processing
Region-based representations of image and video: segmentation tools for multimedia services
IEEE Transactions on Circuits and Systems for Video Technology
Multicore system-on-chip architecture for MPEG-4 streaming video
IEEE Transactions on Circuits and Systems for Video Technology
Predictive watershed: a fast watershed algorithm for video segmentation
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
An introduction to the MPEG-4 animation framework eXtension
IEEE Transactions on Circuits and Systems for Video Technology
Interpolator data compression for MPEG-4 animation
IEEE Transactions on Circuits and Systems for Video Technology
Motion estimation using spatio-temporal contextual information
IEEE Transactions on Circuits and Systems for Video Technology
Enhanced hexagonal search for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
EPIDETOX: an ESL platform for integrated circuit design and tool exploration
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Reconfigurable media coding: An overview
Image Communication
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Concurrently exploring both algorithmic and architectural optimizations is a new design paradigm. This survey paper addresses the latest research and future perspectives on the simultaneous development of video coding, processing, and computing algorithms with emerging platforms that have multiple cores and reconfigurable architecture. As the algorithms in forthcoming visual systems become increasingly complex, many applications must have different profiles with different levels of performance. Hence, with expectations that the visual experience in the future will become continuously better, it is critical that advanced platforms provide higher performance, better flexibility, and lower power consumption. To achieve these goals, algorithm and architecture co-design is significant for characterizing the algorithmic complexity used to optimize targeted architecture. This paper shows that seamless weaving of the development of previously autonomous visual computing algorithms and multicore or reconfigurable architectures will unavoidably become the leading trend in the future of video technology.