Available paralellism in video applications
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Real-Time Parallel MPEG-2 Decoding in Software
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
MPEG-2 Video Decompression on Simultaneous Multithreaded Multimedia Processors
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
Proceedings of the 42nd annual Design Automation Conference
Hierarchical Parallelization of an H.264/AVC Video Encoder
PARELEC '06 Proceedings of the international symposium on Parallel Computing in Electrical Engineering
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications
IISWC '07 Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization
MIPS MT: a multithreaded RISC architecture for embedded real-time processing
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Thread-parallel MPEG-2, MPEG-4 and H.264 video encoders for SoC multi-processor architectures
IEEE Transactions on Consumer Electronics
Performance of software-based MPEG-2 video encoder on parallel and distributed systems
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Generalized B pictures and the draft H.264/AVC video-compression standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
Variable block-size transforms for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard
IEEE Transactions on Circuits and Systems for Video Technology
H.264/AVC baseline profile decoder complexity analysis
IEEE Transactions on Circuits and Systems for Video Technology
Complexity of optimized H.26L video decoder implementation
IEEE Transactions on Circuits and Systems for Video Technology
An evaluation of parallelization concepts for baseline-profile compliant H.264/AVC decoders
Euro-Par'07 Proceedings of the 13th international Euro-Par conference on Parallel Processing
A scalable parallel H.264 decoder on the cell broadband engine architecture
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Circuits and Systems for Video Technology
Development of a high-level simulation approach and its application to multicore video decoding
IEEE Transactions on Circuits and Systems for Video Technology
Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine
Proceedings of the 24th ACM International Conference on Supercomputing
Adaptive multithreaded H.264/AVC decoding
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A QHD-capable parallel H.264 decoder
Proceedings of the international conference on Supercomputing
Evaluation of data-parallel H.264 decoding approaches for strongly resource-restricted architectures
Multimedia Tools and Applications
A highly scalable parallel implementation of h.264
Transactions on High-Performance Embedded Architectures and Compilers IV
Batch-pipelining for multicore H.264 decoding
Journal of Visual Communication and Image Representation
Parallel HEVC Decoding on Multi- and Many-core Architectures
Journal of Signal Processing Systems
Multi-core system performance prediction and analysis at the ESL
International Journal of Computational Science and Engineering
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format
Journal of Signal Processing Systems
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An important question is whether emerging and future applications exhibit sufficient parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future chip multiprocessors (CMPs) are expected to contain. As a case study we investigate the parallelism available in video decoders, an important application domain now and in the future. Specifically, we analyze the parallel scalability of the H.264 decoding process. First we discuss the data structures and dependencies of H.264 and show what types of parallelism it allows to be exploited. We also show that previously proposed parallelization strategies such as slice-level, frame-level, and intra-frame macroblock (MB) level parallelism, are not sufficiently scalable. Based on the observation that inter-frame dependencies have a limited spatial range we propose a new parallelization strategy, called Dynamic 3D-Wave. It allows certain MBs of consecutive frames to be decoded in parallel. Using this new strategy we analyze the limits to the available MB-level parallelism in H.264. Using real movie sequences we find a maximum MB parallelism ranging from 4000 to 7000. We also perform a case study to assess the practical value and possibilities of a highly parallelized H.264 application. The results show that H.264 exhibits sufficient parallelism to efficiently exploit the capabilities of future manycore CMPs.