Exploring design space of parallel realizations: MPEG-2 decoder case study
Proceedings of the ninth international symposium on Hardware/software codesign
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ICS '01 Proceedings of the 15th international conference on Supercomputing
DSTRIDE: data-cache miss-address-based stride prefetching scheme for multimedia processors
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
A survey of processors with explicit multithreading
ACM Computing Surveys (CSUR)
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
A scalable, clustered SMT processor for digital signal processing
MEDEA '03 Proceedings of the 2003 workshop on MEmory performance: DEaling with Applications , systems and architecture
Architecture optimization for multimedia application exploiting data and thread-level parallelism
Journal of Systems Architecture: the EUROMICRO Journal
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Journal of VLSI Signal Processing Systems
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
Parallel Scalability of Video Decoders
Journal of Signal Processing Systems
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This paper explores microarchitecture models for a simultaneous multithreaded processor with multimedia enhancements. We enhance a wide-issue superscalar processor by the simultaneous multithreading technique, by multimedia units, and by an additional on-chip RAM storage. Our workload is a multithreaded MPEG-2 video decompression algorithm that extensively uses multimedia units. Our simulation results suggest that a 2- or 4-threaded 4-issue processor with a small on-chip RAM accessed by a local load/store unit will be superior to a wide-issue (single-threaded) superscalar processor.