Multithreading: a revisionist view of dataflow architectures
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
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ICS '92 Proceedings of the 6th international conference on Supercomputing
The MIT Alewife machine: architecture and performance
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
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Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
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ACM Computing Surveys (CSUR)
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Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
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CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
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ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
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The MIPS® MT architecture is a fine-grained multithreading extension to the general-purpose MIPS RISC architecture. In addition to the classical multithreaded provision for explicit exploitation of cuncurrency as a mechanism for latency tolerance, MIPS MT has unique features to address the problems of real-time and embedded computing in System-on-a-Chip environments. This paper provides an overview of the MIPS MT architecture and how it can variously be exploited to improve computational bandwidth, real time quality of service, and response time to asynchronous events.