Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design

Authors:
Patrick Schaumont;Bo-Cheng Charles Lai;Wei Qin;Ingrid Verbauwhede
Affiliations:
UCLA, CA;UCLA, CA;Boston University, MA;UCLA, CA and ESAT, K.U. Leuven, BE
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 12
Cited 6

Concurrent programming: principles and practice

Concurrent programming: principles and practice
Computer architecture: a quantitative approach

Computer architecture: a quantitative approach
Automatic performance setting for dynamic voltage scaling

Wireless Networks
Simultaneous Multithreading: A Platform for Next-Generation Processors

IEEE Micro
A Scalable High-Performance Computing Solution for Networks on Chips

IEEE Micro
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Application-directed voltage scaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Interactive Cosimulation with Partial Evaluation

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Leakage aware dynamic voltage scaling for real-time embedded systems

Proceedings of the 41st annual Design Automation Conference
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

Selective code/data migration for reducing communication energy in embedded MpSoC architectures

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Supporting task migration in multi-processor systems-on-chip: a feasibility study

Proceedings of the conference on Design, automation and test in Europe: Proceedings
Hardware scheduling support in SMP architectures

Proceedings of the conference on Design, automation and test in Europe
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications

Journal of Signal Processing Systems
Parallel Scalability of Video Decoders

Journal of Signal Processing Systems
Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose an embedded multiprocessor architecture and its associated thread-based programming model. Using a cycle-true simulation model of this architecture, we are able to estimate energy savings for a threaded C program. The savings are obtained by voltage- and frequency-scaling of the individual processors. We port a fingerprint minutiae detection application onto this architecture, and show the resulting performance on single-, dual-, and quad-processor configurations. The energy-scaled quadprocessor version results in a 77% energy reduction over the single-processor non-scaled implementation, at only a 2.2% degradation in cycle count.