Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors

  • Authors:

  • Jaehyun Park;Donghwa Shin;Naehyuck Chang;Massoud Pedram

  • Affiliations:

  • Seoul National University, Seoul, South Korea;Seoul National University, Seoul, South Korea;Seoul National University, Seoul, South Korea;University of Southern California, Los Angeles, CA, USA

  • Venue:
  • Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
  • Year:
  • 2010

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Abstract

Dynamic voltage and frequency scaling (DVS) has been studied for well over a decade, and even commercial systems widely support DVS nowadays. Nevertheless, existing DVS transition overhead models do not accurately reflect modern DVS architectures including modern DC-DC converters, PLL (Phase Lock Loop), and voltage and frequency change policies. Incorrect DVS overhead models prevent one from achieving the maximum energy gain, by misleading the DVS control policies. This paper introduces an accurate DVS overhead model, in terms of both energy consumption and time penalty, through detailed observation of modern DVS setups and voltage and frequency change guidelines from vendors. We introduce new major contributors to the DVS overhead including the performance underdrive loss of the DVS-enabled microprocessor, additional inductor IR loss, and so on, as well as consideration of power efficiency from discontinuous-mode DC-DC conversion. Our DVS overhead model enhances the DVS overhead model accuracy from 86% to 238% for Intel Core2 Duo E6850 and LTC3733.