Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Using multiple energy gears in MPI programs on a power-scalable cluster
Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming
A Power-Aware Run-Time System for High-Performance Computing
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Adaptive, transparent frequency and voltage scaling of communication phases in MPI programs
Proceedings of the 2006 ACM/IEEE conference on Supercomputing
CPU MISER: A Performance-Directed, Run-Time System for Power-Aware Clusters
ICPP '07 Proceedings of the 2007 International Conference on Parallel Processing
Prediction models for multi-dimensional power-performance optimization on many cores
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Evaluating high performance communication: a power perspective
Proceedings of the 23rd international conference on Supercomputing
Adagio: making DVS practical for complex HPC applications
Proceedings of the 23rd international conference on Supercomputing
Energy-Efficient Cluster Computing via Accurate Workload Characterization
CCGRID '09 Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Designing Power-Aware Collective Communication Algorithms for InfiniBand Clusters
ICPP '10 Proceedings of the 2010 39th International Conference on Parallel Processing
Designing Energy Efficient Communication Runtime Systems for Data Centric Programming Models
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer
PACT '11 Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The drive to extract peak performance from the modern computing platforms has lead to drastic increase in their energy and power consumption and thereby affecting the operating costs and failure rates. Modern processors provide techniques, such as dynamic voltage and frequency scaling (DVFS) and CPU clock modulation (called throttling), to improve energy efficiency on-the-fly. Without careful application, however, DVFS and throttling may cause a significant performance loss due to the system overhead. Much research attempts to use these techniques by choosing a performance loss for the application, under which the energy savings are to be obtained. This paper discusses potential pitfalls of the performance-loss approach and proposes a frequency scaling scheme that is based on instantaneous CPU power consumption, and thus, avoids the need for the user to predefine performance tolerance. Preliminary experiments, performed on NAS benchmarks, show that the proposed scheme saves more energy than the approach based on the predefined performance loss.