ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Efficient behavior-driven runtime dynamic voltage scaling policies
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Dynamic voltage frequency scaling for multi-tasking systems using online learning
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Low-overhead design technique for calibration of maximum frequency at multiple operating points
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Static analysis of processor stall cycle aggregation
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Koala: a platform for OS-level power management
Proceedings of the 4th ACM European conference on Computer systems
Energy-Efficient Cluster Computing via Accurate Workload Characterization
CCGRID '09 Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid
System-level power management using online learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple clock and voltage domains for chip multi processors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Predictive-flow-queue-based energy optimization for gigabit ethernet controllers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing
Performance and power modeling in a multi-programmed multi-core environment
Proceedings of the 47th Design Automation Conference
Energy efficient multiprocessor task scheduling under input-dependent variation
Proceedings of the Conference on Design, Automation and Test in Europe
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Memory access aware on-line voltage control for performance and energy optimization
Proceedings of the International Conference on Computer-Aided Design
PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems
ACM Transactions on Embedded Computing Systems (TECS)
Journal of Systems and Software
Speed scaling problems with memory/cache consideration
TAMC'12 Proceedings of the 9th Annual international conference on Theory and Applications of Models of Computation
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Achieving autonomous power management using reinforcement learning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
International Journal of High Performance Computing Applications
E2SC '13 Proceedings of the 1st International Workshop on Energy Efficient Supercomputing
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This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15% ∼ 60% CPU energy saving was achieved at the cost of 5%-20% performance penalty.