The nature of statistical learning theory
The nature of statistical learning theory
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Reliable and energy-efficient digital signal processing
Proceedings of the 39th annual Design Automation Conference
Low-Power CMOS Design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Dynamic complexity scaling for real-time H.264/AVC video encoding
Proceedings of the 15th international conference on Multimedia
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Green: a framework for supporting energy-conscious programming using controlled approximation
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
Best-effort computing: re-thinking parallel software and hardware
Proceedings of the 47th Design Automation Conference
Hardware that produces bounded rather than exact results
Proceedings of the 47th Design Automation Conference
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Leveraging variable function resilience for selective software reliability on unreliable hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and characterization of inherent application resilience for approximate computing
Proceedings of the 50th Annual Design Automation Conference
Quality programmable vector processors for approximate computing
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
On reconfiguration-oriented approximate adder design and its application
Proceedings of the International Conference on Computer-Aided Design
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
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Several recently proposed design techniques leverage the inherent error resilience of applications for improved efficiency (energy or performance). Hardware and software systems that are thus designed may be viewed as "scalable effort systems", since they offer the capability to modulate the effort that they expend towards computation, thereby allowing for tradeoffs between output quality and efficiency. We propose the concept of Dynamic Effort Scaling (DES), which refers to dynamic management of the control knobs that are exposed by scalable effort systems. We argue the need for DES by observing that the degree of resilience often varies significantly across applications, across datasets, and even within a dataset. We propose a general conceptual framework for DES by formulating it as a feedback control problem, wherein the scaling mechanisms are regulated with the goal of maintaining output quality within a certain specified limit. We present an implementation of Dynamic Effort Scaling in the context of a scalable-effort processor for Support Vector Machines, and evaluate it under various application scenarios and data sets. Our results clearly demonstrate the benefits of the proposed approach --- statically setting the scaling mechanisms leads to either significant error overshoot or significant opportunities for energy savings left on the table unexploited. In contrast, DES is able to effectively regulate the output quality while maximally exploiting the time-varying resiliency in the workload.