Best-effort versus reservations: a simple comparative analysis
Proceedings of the ACM SIGCOMM '98 conference on Applications, technologies, architectures, and protocols for computer communication
Best-effort parallel execution framework for Recognition and mining applications
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Best-effort semantic document search on GPUs
Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
Dynamic effort scaling: managing the quality-efficiency tradeoff
Proceedings of the 48th Design Automation Conference
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
Incorrect systems: it's not the problem, it's the solution
Proceedings of the 49th Annual Design Automation Conference
Panacea: towards holistic optimization of MapReduce applications
Proceedings of the Tenth International Symposium on Code Generation and Optimization
Performance, scalability, and semantics of concurrent FIFO queues
ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and characterization of inherent application resilience for approximate computing
Proceedings of the 50th Annual Design Automation Conference
Quality programmable vector processors for approximate computing
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
On reconfiguration-oriented approximate adder design and its application
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
With the advent of mainstream parallel computing, applications can obtain better performance only by scaling to platforms with larger numbers of cores. This is widely considered to be a very challenging problem due to the difficulty of parallel programming and the bottlenecks to efficient parallel execution. Inspired by how networking and storage systems have scaled to handle very large volumes of packet traffic and persistent data, we propose a new approach to the design of scalable, parallel computing platforms. For decades, computing platforms have gone to great lengths to ensure that every computation specified by applications is faithfully executed. While this design philosophy has remained largely unchanged, applications and the basic characteristics of their workloads have changed considerably. A wide range of existing and emerging computing workloads have an inherent forgiving nature. We therefore argue that adopting a best-effort service model for various software and hardware components of the computing platform stack can lead to drastic improvements in scalability. Applications are cognizant of the best-effort model, and separate their computations into those that may be executed on a best-effort basis and those that require the traditional execution guarantees. Best-effort computations may be exploited to simply reduce the computing workload, shape it to be more suitable for parallel execution, or execute it on unreliable hardware components. Guaranteed computations are realized either through an overlay software layer on top of the best-effort substrate, or through the use of application-specific strategies. We describe a system architecture for a best-effort computing platform, provide examples of parallel software and hardware that embody the best-effort model, and show that large improvements in performance and energy efficiency are possible through the adoption of this approach.