Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Multi-media Applications and Imprecise Computation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Best-effort parallel execution framework for Recognition and mining applications
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Green: a framework for supporting energy-conscious programming using controlled approximation
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency
Proceedings of the 47th Design Automation Conference
Best-effort computing: re-thinking parallel software and hardware
Proceedings of the 47th Design Automation Conference
Scalable stochastic processors
Proceedings of the Conference on Design, Automation and Test in Europe
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
ERSA: error resilient system architecture for probabilistic applications
Proceedings of the Conference on Design, Automation and Test in Europe
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
EnerJ: approximate data types for safe and general low-power computation
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Dynamic effort scaling: managing the quality-efficiency tradeoff
Proceedings of the 48th Design Automation Conference
Managing performance vs. accuracy trade-offs with loop perforation
Proceedings of the 19th ACM SIGSOFT symposium and the 13th European conference on Foundations of software engineering
Assuring application-level correctness against soft errors
Proceedings of the International Conference on Computer-Aided Design
Architecture support for disciplined approximate programming
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
Accuracy-configurable adder for approximate arithmetic designs
Proceedings of the 49th Annual Design Automation Conference
Proving acceptability properties of relaxed nondeterministic approximate programs
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Verified integrity properties for safe approximate program transformations
PEPM '13 Proceedings of the ACM SIGPLAN 2013 workshop on Partial evaluation and program manipulation
Neural Acceleration for General-Purpose Approximate Programs
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis and characterization of inherent application resilience for approximate computing
Proceedings of the 50th Annual Design Automation Conference
Paraprox: pattern-based approximation for data parallel applications
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Approximate computing leverages the intrinsic resilience of applications to inexactness in their computations, to achieve a desirable trade-off between efficiency (performance or energy) and acceptable quality of results. To broaden the applicability of approximate computing, we propose quality programmable processors, in which the notion of quality is explicitly codified in the HW/SW interface, i.e., the instruction set. The ISA of a quality programmable processor contains instructions associated with quality fields to specify the accuracy level that must be met during their execution. We show that this ability to control the accuracy of instruction execution greatly enhances the scope of approximate computing, allowing it to be applied to larger parts of programs. The micro-architecture of a quality programmable processor contains hardware mechanisms that translate the instruction-level quality specifications into energy savings. Additionally, it may expose the actual error incurred during the execution of each instruction (which may be less than the specified limit) back to software. As a first embodiment of quality programmable processors, we present the design of Quora, an energy efficient, quality programmable vector processor. Quora utilizes a 3-tiered hierarchy of processing elements that provide distinctly different energy vs. quality trade-offs, and uses hardware mechanisms based on precision scaling with error monitoring and compensation to facilitate quality programmable execution. We evaluate an implementation of Quora with 289 processing elements in 45nm technology. The results demonstrate that leveraging quality-programmability leads to 1.05X-1.7X savings in energy for virtually no loss (