Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
IEEE Transactions on Computers
UMHexagonS Algorithm Based Motion Estimation Architecture for H.264/AVC
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
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Run-time adaptive energy-aware motion and disparity estimation in multiview video coding
Proceedings of the 48th Design Automation Conference
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Proceedings of the 48th Design Automation Conference
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the International Conference on Computer-Aided Design
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The limited energy resources in portable multimedia devices require the reduction of encoding complexity. The complex Motion Estimation (ME) scheme of H.264/MPEG-4 AVC accounts for a major part of the encoder energy [3]. In this paper we present a Run-Time Adaptive Predictive Energy Budgeting (enBudget) scheme for energy-aware ME that predicts the energy budget for different video frames and different Macroblocks (MBs) in an adaptive manner considering the run-time changing scenarios of available energy, video frame characteristics, and user-defined coding constraints while keeping a good video quality. It assigns different Energy-Quality Classes to different video frames and fine-tunes at MB level depending upon the predictive energy quota in order to cope with above-mentioned run-time unpredictable scenarios. Compared to UMHexagonS [4], EPZS [6], and FastME [20], our enBudget scheme for energy-aware ME achieves an energy saving of up to 93%, 90%, 88% (average 88%, 77%, 66%), respectively. It suffers from an average Peak Signal to Noise Ratio (PSNR) loss of 0.29 dB compared to Full Search. We also demonstrate that enBudget is equally beneficial to various other state-of-the-art fast adaptive MEs (e.g. [4]). We have evaluated our scheme for ASIC and various FPGAs.