Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
Process variation tolerant low power DCT architecture
Proceedings of the conference on Design, automation and test in Europe
Variable latency speculative addition: a new paradigm for arithmetic circuit design
Proceedings of the conference on Design, automation and test in Europe
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Real-time H.264 video encoding in software with fast mode decision and dynamic complexity control
ACM Transactions on Multimedia Computing, Communications, and Applications (TOMCCAP)
Proceedings of the Conference on Design, Automation and Test in Europe
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
Modeling and synthesis of quality-energy optimal approximate adders
Proceedings of the International Conference on Computer-Aided Design
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Improving energy gains of inexact DSP hardware through reciprocative error compensation
Proceedings of the 50th Annual Design Automation Conference
Analysis and characterization of inherent application resilience for approximate computing
Proceedings of the 50th Annual Design Automation Conference
On reconfiguration-oriented approximate adder design and its application
Proceedings of the International Conference on Computer-Aided Design
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems
Proceedings of the International Conference on Computer-Aided Design
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
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Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact obviates the need to produce exactly correct numerical outputs. Previous research in this context exploits error-resiliency primarily through voltage over-scaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate Full Adder (FA) cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling. We design architectures for video and image compression algorithms using the proposed approximate arithmetic units, and evaluate them to demonstrate the efficacy of our approach. Post-layout simulations indicate power savings of up to 60% and area savings of up to 37% with an insignificant loss in output quality, when compared to existing implementations.