Adaptive filter theory (3rd ed.)
Adaptive filter theory (3rd ed.)
A New Approach to Pipeline FFT Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Energy Aware Computing through Probabilistic Switching: A Study of Limits
IEEE Transactions on Computers
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Proceedings of the conference on Design, automation and test in Europe
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
IMPACT: imprecise adders for low-power approximate computing
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Proceedings of the 9th conference on Computing Frontiers
A methodology for energy-quality tradeoff using imprecise hardware
Proceedings of the 49th Annual Design Automation Conference
What to do about the end of Moore's law, probably!
Proceedings of the 49th Annual Design Automation Conference
Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
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We present a zero hardware-overhead design approach called reciprocative error compensation (REC) that significantly enhances the energy-accuracy trade-off gains in inexact signal processing datapaths by using a two-pronged approach: (a) deliberately redesigning the basic arithmetic blocks to effectively compensate for each other's (expected) error through inexact logic minimization, and (b) "reshaping" the response waveforms of the systems being designed to further reduce any residual error. We apply REC to several DSP primitives such as the FFT and FIR filter blocks, and show that this approach delivers 2-3 orders of magnitude lower (expected) error and more than an order of magnitude lesser Signal-to-Noise Ratio (SNR) loss (in dB) over the previously proposed inexact design techniques, while yielding similar energy gains. Post-layout comparisons in the 65nm process technology show that our REC approach achieves upto 73% energy savings (with corresponding delay and area savings of upto 16% and 62% respectively) when compared to an existing exact DSP implementation while trading a relatively small loss in SNR of less than 1.5 dB.