Fault-tolerant computing: theory and techniques; Vol. 2
Fault-tolerant computing: theory and techniques; Vol. 2
On Symmetric Error Correcting and all Unidirectional Error Detecting Codes
IEEE Transactions on Computers
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
Journal of Electronic Testing: Theory and Applications
Self-Dual Duplication for Error Detection
ATS '98 Proceedings of the 7th Asian Test Symposium
Accurate and scalable reliability analysis of logic circuits
Proceedings of the conference on Design, automation and test in Europe
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
One-to-Many: Context-Oriented Code for Concurrent Error Detection
Journal of Electronic Testing: Theory and Applications
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
MACACO: modeling and analysis of circuits for approximate computing
Proceedings of the International Conference on Computer-Aided Design
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Synthesizing Parsimonious Inexact Circuits through Probabilistic Design Techniques
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Improving energy gains of inexact DSP hardware through reciprocative error compensation
Proceedings of the 50th Annual Design Automation Conference
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits
Proceedings of the 50th Annual Design Automation Conference
ForTER: a forward error correction scheme for timing error resilience
Proceedings of the International Conference on Computer-Aided Design
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This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.