Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
A high-frequency custom CMOS S/390 microprocessor
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes
Journal of Electronic Testing: Theory and Applications
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Synthesis of Low Power CED Circuits Based on Parity Codes
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors
IEEE Transactions on Dependable and Secure Computing
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Multi-media Applications and Imprecise Computation
DSD '05 Proceedings of the 8th Euromicro Conference on Digital System Design
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Survey of Test Vector Compression Techniques
IEEE Design & Test
Error-Tolerance and Multi-Media
IIH-MSP '06 Proceedings of the 2006 International Conference on Intelligent Information Hiding and Multimedia
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
New Methods of Concurrent Checking (Frontiers in Electronic Testing)
New Methods of Concurrent Checking (Frontiers in Electronic Testing)
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Approximate logic circuits for low overhead, non-intrusive concurrent error detection
Proceedings of the conference on Design, automation and test in Europe
Temperature-aware test scheduling for multiprocessor systems-on-chip
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IBM S/390 parallel enterprise server G5 fault tolerance: a historical perspective
IBM Journal of Research and Development
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Concurrent Error Detection (CED) methods provide some level of error detection capability at the cost of some area and power overhead. Incorporating CED schemes into Integrated Circuits (ICs) is becoming increasingly more important, as the continuous technology scaling leads to an ever-higher transient error-related failure rate. For many applications, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for ICs. While duplication provides high CED coverage, its power budget requirement of having two circuits operate all the time limits its application. The key idea of reconfiguration is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using random and judicious selection of control conditions indicate that power dissipation is commensurate with CED coverage, supporting the use of LFSR structures to easily generate and adjust conditions dynamically to adapt to the power constraints of the system during its operation. Moreover, online testing using nonidentical input vectors can also be incorporated, improving the tradeoff between power dissipation and CED coverage.