Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
A framework for satisfying input and output encoding constraints
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Design of Self-Checking Circuits Using DCVS Logic: A Case Study
IEEE Transactions on Computers
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Designing an Asynchronous Communications Chip
IEEE Design & Test
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme
IEEE Transactions on Computers
Synthesis of Asynchronous State Machines Using A Local Clock
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Membership Test Logic for Delay-Insensitive Codes
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
16.1 Novel Single and Double Output TSC Berger Code Checkers
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
On-Line Testing of Globally Asynchronous Circuits
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Low-Cost Online Testing of Asynchronous Handshakes
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Synthesis of Asynchronous Machines Using Mixed-Operation Mode
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact two-level minimization of hazard-free logic with multiple-input changes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft-error tolerance and mitigation in asynchronous burst-mode circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Journal of Electronic Testing: Theory and Applications
Input vector monitoring on line concurrent BIST based on multilevel decoding logic
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Output feedback control of asynchronous sequential machines with disturbance inputs
Information Sciences: an International Journal
| Hi-index | 14.98 |
Asynchronous controllers exhibit various characteristics that limit the effectiveness and applicability of the Concurrent Error Detection (CED) methods developed for their synchronous counterparts. Asynchronous Burst-Mode Machines (ABMMs), for example, do not have a global clock to synchronize the ABMM with the additional circuitry that is typically used by synchronous CED methods (for example, duplication). Therefore, performing effective CED in ABMMs requires a synchronization method that will appropriately enable the checker (for example, comparator) in order to avoid false alarms. Also, ABMMs contain redundant logic, which guarantees the hazard-free operation required for correct interaction between the circuit and its environment. Redundant logic, however, allows some single event transients to manifest themselves only as hazards but not as logic discrepancies. Therefore, performing effective CED in ABMMs requires the ability to detect hazards with which synchronous CED methods are not concerned. In this work, we first devise hardware solutions for performing checking synchronization and hazard detection. We then demonstrate how these solutions enable the development of three complete CED methods for ABMMs. The first method (Duplication-based CED) is an adaptation of the well-known duplication method within the context of ABMMs. The second method (Transition-Triggered CED) is a variation of duplication wherein the implementation cost is reduced by allowing hazards in the duplicate circuit. In contrast to these two methods, which are nonintrusive, the third method (Berger code-based CED) is intrusive since it requires reencoding of the ABMM with check symbols based on the Berger code. Although this intrusiveness may slightly impact performance, Berger code-based CED incurs the lowest area overhead among the three methods, as indicated through experimental results.