Performance-driven synthesis of asynchronous controllers
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Practical advances in asynchronous design and in asynchronous/synchronous interfaces
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification
Semi-modular Latch Chains for Asynchronous Circuit Design
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
From STG to Extended-Burst-Mode Machines
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Algorithms for the optimal state assignment of asynchronous state machines
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Asynchronous Microengines for Efficient High-level Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Design and Analysis of a Self-Timed Duplex Communication System
IEEE Transactions on Computers
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
Conditional partial order graphs and dynamically reconfigurable control synthesis
Proceedings of the conference on Design, automation and test in Europe
Desynchronisation Technique Using Petri Nets
Electronic Notes in Theoretical Computer Science (ENTCS)
Automatic synthesis of computation interference constraints for relative timing verification
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Dual-rail asynchronous logic multi-level implementation
Integration, the VLSI Journal
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