Communicating sequential processes
Communicating sequential processes
Three partition refinement algorithms
SIAM Journal on Computing
An implementation of an efficient algorithm for bisimulation equivalence
Science of Computer Programming
A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Computer-aided synthesis and verification of gate-level timed circuits
Computer-aided synthesis and verification of gate-level timed circuits
Communicating sequential processes
Communications of the ACM
Communication and Concurrency
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Synthesis of Timed Asynchronous Circuits
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
"On the Fly" Verification of Behavioural Equivalences and Preorders
CAV '91 Proceedings of the 3rd International Workshop on Computer Aided Verification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Designing Fast Asynchronous Circuits
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Relative Timing Based Verification of Timed Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Energy and Performance Models for Clocked and Asynchronous Communication
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
The Family of 4-phase Latch Protocols
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of low energy, high performance synchronous and asynchronous 64-point FFT
Proceedings of the Conference on Design, Automation and Test in Europe
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Asynchronous sequential circuit or protocol design requires formal verification to ensure correct behavior under all operating conditions. However, most asynchronous circuits or protocols cannot be proven conformant to a specification without adding timing assumptions. Relative Timing (RT) is an approach to model and verify circuits and protocols that require timing assumptions to operate correctly. The process of creating path-based RT constraints has previously been done by hand with the aid of a formal verification engine. This time consuming and error prone method vastly restricts the application of RT and the capability to implement circuits and protocols. This paper describes an algorithm for automatic generation of RT constraints based on signal traces generated from a formal verification (FV) engine that supports relative timing constraints. This algorithm has been implemented in a CAD tool called Automatic Relative Timing Identifier based on Signal Traces (ARTIST) which has been embedded into the FV engine. A set of asynchronous and clocked designs and protocols have been verified and proven to be hazard-free with the RT constraints generated by ARTIST which would have taken months to perform by hand. A comparison of RT constraints between hand-generated and ARTIST generated constraints is also described in terms of efficiency and quality.