Design of asynchronous circuits by synchronous CAD tools
Proceedings of the 39th annual Design Automation Conference
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Automatic synthesis of computation interference constraints for relative timing verification
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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A five-step design process for asynchronous circuits helps simplify their logic and speed their operation. First, assume that all logic gates in the control will have nearly uniform delay. Second, use the uniform delay assumption to simplify control logic. Third, lay out the chip to get wire length data. Fourth, choose a specific delay and calculate transistor widths to apply that specific delay uniformly to all logic gates in the control; this paper shows how. Fifth, verify correct operation with standard methods. The specific gate delay trades off speed, area, and power consumption; postponing its choice takes advantage of asynchrony to accommodate the limitations imposed by layout. The theoretical lower bound for specific delay depends on the logical effort of the most complex loop in the design and remarkably, is independent of wire capacitance, given wide enough transistors, but wire capacitance puts practical bounds on speed. The effect of wire resistance remains unexplored.