Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Delay-insensitive multi-ring structures
Integration, the VLSI Journal - Special issue on asynchronous systems
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Designing Fast Asynchronous Circuits
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
AMULET3: A 100 MIPS Asynchronous Embedded Processor
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Glitch-free design for multi-threshold CMOS NCL circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Performance-driven clustering of asynchronous circuits
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
MTD3L: a secure IC design methodology with reduced overhead
ACMIN'12 Proceedings of the 14th international conference on Automatic Control, Modelling & Simulation, and Proceedings of the 11th international conference on Microelectronics, Nanoelectronics, Optoelectronics
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
| Hi-index | 0.00 |
Poor CAD support hinders wide acceptance of asynchronous methodologies, and asynchronousdesign tools are far behind synchronous commercial tools. A new design flow, NCL_X, based entirely on commercial CAD tools, targets a subclass of asynchronous circuits called null convention logic. NCL_X shows significant area improvement over other flows for this subclass.EDA FLOWS are industry driven and thus use synchronous methodologies as de facto standards. However implementation problems arise from imposing a synchronous model of operation on deep-submicron circuits. This problem motivates the investigation of other asynchronous modes of operation. Acceptance of new design methodologies including asynchronous ones engineering and industrial communities depends on three major issues:added value of the methodology in terms ofareapowerspeedelectromagnetic interference (EMI) noise immunityand so on; tradeoffs whichdesignparametersoften worsen to achieve added valuessuch as speed versus power and area versusEMI; and the cost of switching to the new methodology including training time development of new libraries and time spent dealing with CAD tool immaturity.