Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
On the models for asynchronous circuit behaviour with OR causality
Formal Methods in System Design
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Designing an Asynchronous Microcontroller Using Pipefitter
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACSD '07 Proceedings of the Seventh International Conference on Application of Concurrency to System Design
Workcraft: a static data flow structure editing, visualisation and analysis tool
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Average-case technology mapping of asynchronous burst-mode circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Direct Mapping of Low-Latency Asynchronous Controllers From STGs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A token-based model for asynchronous data path, called static data flow structures (SDFS), is formally defined. Three token game semantics are introduced for this model, namely atomic token, spread token and counterflow. The SDFS semantics are analysed using a simple benchmark example; their advantages and drawbacks are highlighted. A combination of spread token and counterflow models, which employs the advantages of both, is presented. A technique is described for mapping the high-level SDFS token game semantics into the low level of underlying Petri nets (PNs). The PNs are employed as a back-end for verification of SDFS models. For analysis and comparison of SDFS semantics a software tool has been developed, which integrates all SDFS semantics into a consistent framework, implements their conversion into PNs and provides an interface to existing model checking tools.