An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Design of asynchronous circuits by synchronous CAD tools
Proceedings of the 39th annual Design Automation Conference
The Design of Rijndael
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
SPA " A Synthesisable Amulet Core for Smartcard pplications
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
An Investigation into the Security of Self-Timed Circuits
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Masking the Energy Behavior of DES Encryption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Dynamic differential self-timed logic families for robust and low-power security ICs
Integration, the VLSI Journal
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Remote Password Extraction from RFID Tags
IEEE Transactions on Computers
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
Evaluating the robustness of secure triple track logic through prototyping
Proceedings of the 21st annual symposium on Integrated circuits and system design
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Novel PUF-Based Error Detection Methods in Finite State Machines
Information Security and Cryptology --- ICISC 2008
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
Electronic Notes in Theoretical Computer Science (ENTCS)
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Proceedings of the Conference on Design, Automation and Test in Europe
When failure analysis meets side-channel attacks
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
On side-channel resistant block cipher usage
ISC'10 Proceedings of the 13th international conference on Information security
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Formal evaluation of the robustness of dual-rail logic against DPA attacks
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Analysis and improvement of dual rail logic as a countermeasure against DPA
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
| Hi-index | 14.99 |
Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method and the tool.