Formal evaluation of the robustness of dual-rail logic against DPA attacks

Authors:
Alin Razafindraibe;Michel Robert;Philippe Maurine
Affiliations:
Microelectronics Department, LIRMM, Montpellier, France;Microelectronics Department, LIRMM, Montpellier, France;Microelectronics Department, LIRMM, Montpellier, France
Venue:
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2006

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Abstract

Based on a first order model of the switching current flowing in CMOS cell, an investigation of the robustness against DPA of dual-rail logic is carried out. The result of this investigation, performed on 130nm process, is a formal identification of the design range in which dual-rail logic can be considered as robust.