Evaluating the robustness of secure triple track logic through prototyping

Authors:
Rafael Soares;Ney Calazans;Victor Lomné;Philippe Maurine;Lionel Torres;Michel Robert
Affiliations:
Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil;Pontifícia Universidade Católica do Rio Grande do Sul, Porto Alegre, Brazil;Université Montpellier 2, Montpellier, France;Université Montpellier 2, Montpellier, France;Université Montpellier 2, Montpellier, France;Université Montpellier 2, Montpellier, France
Venue:
Proceedings of the 21st annual symposium on Integrated circuits and system design
Year:
2008

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Abstract

Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, this paper proposes to prototype a logic called Secure Triple Track Logic (STTL) on FPGA and evaluate its robustness against power analyses. More precisely, the paper aims at demonstrating that the basic concepts on which this logic leans are valid and may provide interesting design guidelines to obtain secure circuits.