Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Power Attacks on Secure Hardware Based on Early Propagation of Data
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A design methodology for secured ICs using dynamic current mode logic
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
The “backend duplication” method
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Evaluating the robustness of secure triple track logic through prototyping
Proceedings of the 21st annual symposium on Integrated circuits and system design
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Proceedings of the Conference on Design, Automation and Test in Europe
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Cryptographic hardware is vulnerable to power analysis attacks. To resist these attacks, special balanced dual-rail gates have been developed which have equal power consumption for all valid data values and transitions. A limitation of existing designs is that they require balanced routing of the dual-rail interconnect between gates. Natural process variation and suboptimal routing tools make it practically impossible to perfectly match the capacitances of the dual-rail pair making the balanced routing constraint difficult to satisfy. We present a general method and designs which achieve power balance in dual-rail circuits without requiring matching of gate output load capacitances or random masking. The method and design are based on a directional discharge protocol which ensures that both rails are always fully discharged and charged in each cycle.