CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Electromagnetic Analysis: Concrete Results
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
CMOS Structures Suitable for Secured Hardware
Proceedings of the conference on Design, automation and test in Europe - Volume 2
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 44th annual Design Automation Conference
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
IEEE Design & Test
Power balanced gates insensitive to routing capacitance mismatch
Proceedings of the conference on Design, automation and test in Europe
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Physical Design of FPGA Interconnect to Prevent Information Leakage
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Evaluation of Random Delay Insertion against DPA on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Countering early evaluation: an approach towards robust dual-rail precharge logic
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Power analysis of single-rail storage elements as used in MDPL
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
Analysis of nonparametric estimation methods for mutual information analysis
ICISC'10 Proceedings of the 13th international conference on Information security and cryptology
Design and characterisation of an AES chip embedding countermeasures
International Journal of Intelligent Engineering Informatics
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
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Several types of logic gates suitable for leakage-proof computations have been put forward[1,2,3,4]. This paper describes a method, called “backend duplication” to assemble secured gates into leakage-proof cryptoprocessors. To the authors' knowledge, this article is the first CAD-oriented publication to address all the aspects involved in the backend design of secured hardware. The “backend duplication” method achieves the place-and-route of differential netlists. It allows for 100 % placement density and for balanced routing of dual-rail signals. Wires of every other metal layer are free to make turns. In addition, the method does not require any modification to the design rules passed to the router. The “backend duplication” method has been implemented in 0.13 μm ASIC technology and successfully tested on various ciphers. The example of the design of a DES module resistant against side-channel attacks is described into details.