CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
An Implementation of DES and AES, Secure against Some Attacks
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power Attacks on Secure Hardware Based on Early Propagation of Data
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
IEEE Transactions on Computers
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs
SSIRI '08 Proceedings of the 2008 Second International Conference on Secure System Integration and Reliability Improvement
Security Evaluations of MRSL and DRSL Considering Signal Delays
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
Place-and-route impact on the security of DPL designs in FPGAs
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Mutual Information Analysis: How, When and Why?
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
WDDL is Protected against Setup Time Violation Attacks
FDTC '09 Proceedings of the 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography
Power analysis attacks on MDPL and DRSL implementations
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints
Proceedings of the Conference on Design, Automation and Test in Europe
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
The “backend duplication” method
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology
Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems
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Wave Dynamic Differential Logic (WDDL) is a hiding countermeasure to thrawt side channel attacks (SCA). It suffers from a vulnerability called Early Evaluation, i.e. calculating output before all inputs are valid. This causes delay biases in WDDL even when synthesized with positive gates. s a consequence, the design can be attacked, although with extra effort, through side channel. However, WDDL is an appealing logic since it has already been reported to natively resist against multiple asymmetric faults. In this article, we suggest a Dual Rail Precharge Logic (DPL), similar to WDDL, free from early evaluation by design. We demonstrate practically that the early evaluation accounts for major part of the leakage. We also provide basic guidelines for designing such a DPL. This DPL can resist against side channel attacks and fault attacks at the same time. In line with the current security evaluation methodology, we use differential power analysis and mutual information to compare the modified WDDL with the traditional WDDL. To compare robustness w.r.t security, we conduct a proof-of-concept experiment that compares the two logics with identical implementations (P&R) apart from the logic style. The sensitive side channel leakage is reduced by half in the DPL without the early evaluation flaw.