A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Leakage Analysis of DPA Countermeasures at the Logic Level
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Dual-rail random switching logic: a countermeasure to reduce side channel leakage
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Countering early evaluation: an approach towards robust dual-rail precharge logic
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
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In recent years, some countermeasures have been proposed against differential power analysis (DPA) at the basic composition element level of logic circuits. We propose a countermeasure named random switching logic (RSL). RSL involves computation with data masking using a single logic gate and suppression of transient transitions using ENABLE signals generated independently of input data. Recently, some countermeasures that were proposed against DPA, such as MRSL and DRSL, adopted the concept of RSL. Although MRSL is based on RSL, it uses a different method to suppress the transient transitions. DRSL uses RSL to avoid the possibility of leakage caused by a difference in delays occurring in MDPL that combines dual-rail circuits with random masking. The important difference between these countermeasures and RSL is that they can vary the output transition timing depending on the input data patterns. In this paper, we focus on this feature to evaluate the DPA resistance of MRSL and DRSL. Experiments are also conducted on DPA resistance by using an FPGA to verify the evaluation results. It is confirmed that in both MRSL and DRSL, there is a possibility of leakage if a sufficient difference in delays exists in input signals.