Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Security Evaluations of MRSL and DRSL Considering Signal Delays
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Practical Attacks on Masked Hardware
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Fault Analysis Attack against an AES Prototype Chip Using RSL
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Power analysis of single-rail storage elements as used in MDPL
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Lightweight cryptography and DPA countermeasures: a survey
FC'10 Proceedings of the 14th international conference on Financial cryptograpy and data security
Correlation power analysis based on switching glitch model
WISA'10 Proceedings of the 11th international conference on Information security applications
Combination of SW countermeasure and CPU modification on FPGA against power analysis
WISA'10 Proceedings of the 11th international conference on Information security applications
Security evaluation of a DPA-Resistant s-box based on the fourier transform
ICICS'09 Proceedings of the 11th international conference on Information and Communications Security
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a new countermeasure, Random Switching Logic (RSL), against DPA (Differential Power Analysis) and Second-Order DPA at the logic level. RSL makes a signal transition uniform at each gate and suppresses the propagation of glitch to allow power consumption to be independent of predictable data. Furthermore, we implement basic logic circuits on the FPGA (Field Programmable Gate Array) by using RSL, and evaluate the effectiveness. As a result, we confirm the fact that the secure circuit can be structured against DPA and Second-Order DPA.