CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
On Boolean and Arithmetic Masking against Differential Power Analysis
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Using Second-Order Power Analysis to Attack DPA Resistant Software
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Differential Power Analysis in the Presence of Hardware Countermeasures
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Sound Method for Switching between Boolean and Arithmetic Masking
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-Speed True Random Number Generation with Logic Gates Only
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Attack and Improvement of a Secure S-Box Calculation Based on the Fourier Transform
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Superscalar coprocessor for high-speed curve-based cryptography
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 µP
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Security evaluation of a DPA-Resistant s-box based on the fourier transform
ICICS'09 Proceedings of the 11th international conference on Information and Communications Security
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
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This paper presents a design flow for secure software (SW) implementations of cryptographic algorithms against Side-Channel Attacks (SCAs) by using a CPU modification. The development of countermeasures to increase resistance against the SCAs in SW implementations is a topic of ongoing research. Researchers have proposed SW-level countermeasures in order to defeat the SCAs. However, we notice that more secure SW implementations are possible with an additional support from a hardware (HW) level countermeasure such as partial CPU modifications. This paper proposes a co-design approach of SW-level countermeasures and CPU modifications to defeat the SCAs on Field Programmable Gate Arrays (FPGA). As a case study of evaluating an effectiveness of the combination of our SW-/HW-level countermeasures, the S-box algorithm proposed by Coron et al. [1] is used. According to our experimental results, we find that the algorithm can be performed with a higher resistance against power analysis by applying our countermeasures. Our proposed design flow is applicable to various kinds of algorithms as well.