A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

Authors:
Kris Tiri;Ingrid Verbauwhede
Affiliations:
-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Year:
2004

Citing 3
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Abstract

This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make new'compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.