Transient power supply current monitoring—a new test method for CMOS VLSI circuits
Journal of Electronic Testing: Theory and Applications
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
ACM Transactions on Embedded Computing Systems (TECS)
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library
ACSD '05 Proceedings of the Fifth International Conference on Application of Concurrency to System Design
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A design methodology for secured ICs using dynamic current mode logic
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Unclonable Lightweight Authentication Scheme
ICICS '08 Proceedings of the 10th International Conference on Information and Communications Security
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
PUF-HB: a tamper-resilient HB based authentication protocol
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
An automatic design flow for implementation of side channel attacks resistant crypto-chips
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Hi-index | 0.00 |
Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reliability methods are used primarily only to ensure the correctness of the logical functionality and not the balance of a circuit. Due to the hardware redundancy in balanced gate designs, there are many faults which can imbalance a balanced gate without causing logical errors. As a result, traditional testing and reliability methods and architectures are unable to test and verify if a gate is completely defect and fault-free and hence balanced. Our simulations show that a few faulty balanced gates can make a circuit as vulnerable to power analysis attacks as a completely imbalanced implementation. This vulnerability opens the possibility of new methods of attacks based on a combination of fault and power attacks. A solution to the vulnerability based on a built-in differential self-balance comparator is presented.