Proceedings of the 38th annual Design Automation Conference
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Proceedings of the 40th annual Design Automation Conference
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Synthesis of Asynchronous VLSI Circuits
Synthesis of Asynchronous VLSI Circuits
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Differential fault analysis on AES key schedule and some countermeasures
ACISP'03 Proceedings of the 8th Australasian conference on Information security and privacy
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
DPA on faulty cryptographic hardware and countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
A design methodology for secured ICs using dynamic current mode logic
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A fast and accurate power estimation methodology for QDI asynchronous circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Low power asynchronous circuit back-end design flow
Microelectronics Journal
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Regarding the significant mathematical immunity of recent cryptographic algorithms, attacks considering the physical aspects of these algorithms, known as side channel attacks, have received much of interest. Today, it is quite clear that asynchronous circuits possess considerable inherent countermeasure capabilities against side channel attacks, and therefore they are more immune for cryptographic systems compared to synchronous design. However, due to lack of automatic synthesis and optimization tools for these circuits, implementation of secure asynchronous circuits encounters many difficulties. In this paper, a fully automated secure design flow and a set of secure library cells resistant to power analysis and fault injection attacks are introduced for quasi delay insensitive asynchronous circuits. In the proposed flow, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits directly mappable to predefined circuit templates. With the use of a special standard-cell library, the final circuit is resistive to differential power analysis on faulty hardware attack. We suggest a restructuring on the conditional statements in the high-level description of the circuit which leads to a considerable optimization in power consumption after the decomposition of the system. To verify the efficiency of our presented design flow, we implemented data encryption standard (DES) and advanced encryption standard (AES) algorithms, and we showed 23% less power consumption compared to the existing data driven decomposition asynchronous synthesis method. Also, these implementations are three times faster than the synchronous implementations on average, in TSMC 0.18@mm technology.