Communicating sequential processes
Communications of the ACM
Synthesis of Asynchronous VLSI Circuits
Synthesis of Asynchronous VLSI Circuits
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
Diagnosis of faults in template-based asynchronous circuits
SOC'09 Proceedings of the 11th international conference on System-on-chip
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
Journal of Systems Architecture: the EUROMICRO Journal
Low power asynchronous circuit back-end design flow
Microelectronics Journal
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An automatic design flow for implementation of side channel attacks resistant crypto-chips
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A fast and accurate power estimation methodology for QDI asynchronous circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.