Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A co-synthesis approach to embedded system design automation
Design Automation for Embedded Systems
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Proceedings of the 40th annual Design Automation Conference
High-level synthesis of asynchronous systems by data-driven decomposition
Proceedings of the 40th annual Design Automation Conference
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologies
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Design of dual threshold voltages asynchronous circuits
Proceedings of the 13th international symposium on Low power electronics and design
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper introduces a framework for the synthesis of low leakage power asynchronous circuits while maintaining performance requirements. In the proposed framework, a high-level description of the system is received and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The leakage reduction is done via simultaneous supply voltage selection, multiple threshold voltage assignment and template sizing. The power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 90nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty.