Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current estimation of CMOS circuit with stack effect
Journal of Computer Science and Technology - Special issue on computer graphics and computer-aided design
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 13th international symposium on Low power electronics and design
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-threshold pass-transistor logic design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power asynchronous circuit back-end design flow
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Addresses the problem of delay constrained minimization of standby power of CMOS digital circuits that are implemented with dual-Vt technology. The availability of two or more threshold voltages on the same chip provides a new opportunity for circuit designers to make tradeoffs between power and delay. Three efficient algorithms that operate on a gate level netlist are described. Each algorithm assigns one of two threshold voltages (high and low Vt) to each transistor so that the standby power dissipation is minimized without violating a user specified delay constraint. Experimental results on the MCNC91 benchmark circuits show that up to one order of magnitude power reduction can be achieved without any increase in delay when compared to the configuration in which all devices are at the low Vt